The present invention relates, in general, to accessing I/O functions. More specifically, the invention relates to accessing a great variance of I/O devices in a control system. Still more specifically, the present invention deals with accessing such I/O functions in embedded control environments.
In embedded control applications it is not always possible to meet all wanted requirements with standard I/O chips. Very often, it is tried to fulfill these requirements with a custom design. This design then will end in realization of a special designed chip, based, e.g., on ASICs. However, typically the I/O connectivity of these chips and not the available space is limiting the integration of more functionality on the same chip.
Though I/O devices may have a high similarity according to their requirements with regard to the I/O protocols supported (e.g., IC bus (I2C), Universal Asynchronous Receiver/Transmitter (UART), General Purpose I/O (GPI/O) and the like), the number of I/O ports is different on each specific device.
In many applications, a certain number and type of I/O devices must be controlled (it is of no importance whether these devices are cards in a computer system, switches or hub-devices in a network or switching units in a luggage or parcel sorting system or similar systems). Typically, this controlling task is done by means of a microcontroller. However, in most cases, the industry does not offer out of the shelf a respective controller with enough or exactly the right I/O interfaces on the core chip. Accordingly, a chip (most probably an ASIC) will have to be developed that can be connected to the I/O space (memory mapped I/O, PCI, CAN-bus, Ethernet, etc.) of the controller as an extender chip. As already mentioned above, this chip would most probably be a custom design and is expanding the number and the type of the controller interfaces in order to exactly offer the right number and type of interfaces as required by the devices to perform their specific tasks. However, even if all of these devices would need the same sort or type of I/O interfaces (such as GPI/O, UART, IIC, and the like), the quantity of the interfaces may be different for each of the different device types to be controlled. The traditional methods to solve this problem would be to a) develop one individual chip (ASIC) for each device type or, b) develop one single chip (ASIC) providing a superset (in number and type) of all the interfaces needed for all the different device types.
The disadvantage of solution a) is obvious as it is clear that developing and producing n (assumed n being the number of different device types that shall be controlled) different chips (ASICs) is much more expensive then doing all this just once for one chip being produced in bigger volumes.
However, using solution b) would not only maximize the number of transistors on the chip, but would at the same time maximize the number of pins. Since industry is able to double the transistor density on a chip about every 18 months, the number of I/O pins is more and more determining the size and at the same time the costs (for each individual chip as well as for the space in the cards) of a chip.